Improvement of data retention time in DRAM using recessed channel array transistors with asymmetric channel doping for 80 nm feature size and beyond

A 512 Mb DRAM using a recessed channel array transistor with asymmetric channel doping scheme (RCAT-ASC) is fabricated for the first time with 80 nm feature size. We have found that RCAT-ASC shows much better device performance than the normal RCAT-SC (recessed channel array transistor with symmetric channel doping scheme) or PCAT-ASC (planar channel array transistor with asymmetric channel doping scheme). The RCAT-ASC has the lowest junction leakage currents at storage nodes among them. The increase of data retention time is found to be very remarkable, and thus we suggest that the RCAT-ASC should be an effective method for longer data retention time of DRAM for the future generations. Additionally, we also found that the charge sharing time (tCS) of RCAT-ASC has the lowest values among the three array transistor schemes.