Title :
Dual supply voltage clocking for 5 GHz 130 nm integer execution core
Author :
Krishnamurthy, R.K. ; Hsu, S. ; Anders, M. ; Bloechel, B. ; Chatterjee, B. ; Sachdev, M. ; Borkar, S.
Author_Institution :
Circuits Res., Intel Corp., Hillsboro, OR, USA
Abstract :
This paper describes dual-V/sub cc/ clocking on a 1.2 V, 5 GHz integer execution core fabricated in 130 nm CMOS to achieve up to 71% measured clock power (including 15% active leakage) reduction. A write-port style pass-transistor latch and split-output level-converting local clock buffer are described for robust, DC power free low-V/sub cc/ clock operation.
Keywords :
CMOS digital integrated circuits; VLSI; high-speed integrated circuits; microprocessor chips; synchronisation; timing; 1.2 V; 130 nm; 5 GHz; CMOS technology; dual supply voltage clocking; dual-V/sub cc/ clocking; integer execution core; level-converting local clock buffer; split-output local clock buffer; write-port style pass-transistor latch; CMOS technology; Clocks; Degradation; IEC standards; Inverters; Jitter; Latches; Logic; Robustness; Voltage;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7310-3
DOI :
10.1109/VLSIC.2002.1015121
