Production Worthy 3D Interconnect Technology

Author

Tu, H.J. ; Wu, W.J. ; Hu, J.C. ; Yang, K.F. ; Chang, H.B. ; Chiou, W.C. ; Yu, C.H.

Author_Institution

Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), No. 8, Li-Shin Rd. 6, Science Based Industrial Park, Hsinchu, Taiwan 300-77, R.O.C., Phone: 886-3-505-4769 Fax: 886-3-5637000 Email: hjtua@tsmc.com

fYear

2008

fDate

1-4 June 2008

Firstpage

37

Lastpage

39

Abstract

A three dimensional integrated circuit (3DIC) integration flow, process and electrical results are reported. Well-controlled high aspect ratio (AR=8:1 and AR=15:1) through silicon vias (TSVs) were successfully filled with both copper (Cu) and tungsten (W). Metal to metal diffusion bonding was demonstrated with good uniformity and resulted in good electrical performance. For the first time, a cost effective wafer thinning without decreasing effective area by a proprietary process is described. By wafer level electrical testing, yielding 20K through silicon vias with aspect ratio of 15:1 and resistance of through silicon via chain are demonstrated.

Keywords

Copper; Costs; Diffusion bonding; Electric resistance; Integrated circuit interconnections; Integrated circuit technology; Production; Silicon; Testing; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2008. IITC 2008. International

Conference_Location

Burlingame, CA, USA

Print_ISBN

978-1-4244-1911-1

Electronic_ISBN

978-1-4244-1912-8

Type

conf

DOI

10.1109/IITC.2008.4546918

Filename

4546918