DocumentCode
1904873
Title
Low-k dielectric reliability: impact of test structure choice, copper and integrated dielectric quality
Author
Tokei, Zs ; Li, Y.-L. ; Ciofi, I. ; Croes, K. ; Beyer, G.P.
Author_Institution
IMEC, Kapeldreef 75, B-3001 Leuven (Belgium), Phone: +32-16-28.17.78, Fax: +32-16-28.17.06, E-mail: Zsolt.Tokei@imec.be
fYear
2008
fDate
1-4 June 2008
Firstpage
111
Lastpage
113
Abstract
As dielectric spacing between adjacent copper wires scales below 50nm, back-end-of-line dielectric reliability is becoming an increasingly important challenge both for advanced logic and memory devices. It is crucial to understand which physical mechanisms are relevant, because this has an impact on modeling and prediction. In this contribution test methods, test structures and physical mechanisms are discussed.
Keywords
Capacitors; Copper; Dielectric devices; Dielectric materials; Moisture; Packaging; Paramagnetic resonance; Testing; Vehicles; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology Conference, 2008. IITC 2008. International
Conference_Location
Burlingame, CA, USA
Print_ISBN
978-1-4244-1911-1
Electronic_ISBN
978-1-4244-1912-8
Type
conf
DOI
10.1109/IITC.2008.4546940
Filename
4546940
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