Investigation of the impact of CoWp self-aligned barrier deposition on the porous siOC properties after a direct CMP process

To reduce the capacitance and mimprove the reliability of metal interconnects at the 32 nm node and beyond, a promising approach is to use a direct CMP process stopping in the porous ultra-low k material combined with a metallicself-aligned CoWP capping layer. We demonstrate on 45 nm technology node wafers, that our self-aligned barrier layer process is compatible with the direct CMP process.