Title :
The application of lithography defect simulation to submicron CMOS yield improvement efforts
Author :
Milor, Linda ; Orth, Jonathan ; Steele, Dave ; Phan, Khoi ; Li, Xiaolei ; Strojwas, Andrzej ; Lin, Yung-Tao
Author_Institution :
Submicron Dev. Center, Adv. Micro Devices Inc., Sunnyvale, CA, USA
Abstract :
Yield improvement efforts traditionally involve extensive experimental work aimed at diagnosing defects. This paper proposes supplementing such experimental work with defect simulation. An example of identifying a defect in the top antireflective coating (TARC) on photoresist illustrates yield improvement efforts involving both defect simulations and experimentation
Keywords :
CMOS integrated circuits; digital simulation; integrated circuit yield; photolithography; surface topography; METROPOLE topography simulator; lithography defect simulation; photoresist antireflective coating; submicron CMOS yield improvement; Circuit optimization; Circuit simulation; Coatings; Computational modeling; Computer simulation; Costs; Light scattering; Lithography; Particle scattering; Resists;
Conference_Titel :
Semiconductor Manufacturing Conference Proceedings, 1997 IEEE International Symposium on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-3752-2
DOI :
10.1109/ISSM.1997.664587
