GA-based architecture exploration method for low energy VLIW data-path model

Author

Aoki, Kazuo ; Taniguchi, Ittetsu ; Tomiyama, Hiroyuki ; Fukui, M.

Author_Institution

Grad. Sch. of Sci. & Eng., Ritsumeikan Univ., Kusatsu, Japan

fYear

2013

fDate

4-6 Sept. 2013

Firstpage

307

Lastpage

310

Abstract

In this paper, we propose GA-based architecture exploration method for high performance and low energy VLIW data-path. Contribution of this paper is a method to find Pareto optimal FU architecture, i.e., the number of FUs and the instruction assignment for each FU. Proposed method enables to explore the vast solution space effectively, and we obtained the almost optimal Pareto curves for real life applications for about five times faster than the exhaustive search base method. The exploration error on cycle vs energy Pareto curve was less than 1%.

Keywords

Pareto optimisation; genetic algorithms; instruction sets; low-power electronics; parallel architectures; power aware computing; GA-based architecture exploration method; Pareto curve; Pareto optimal FU architecture; exploration error; instruction assignment; low energy VLIW data path model; Benchmark testing; Cavity resonators; Computer architecture; Educational institutions; Energy consumption; Estimation; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Information Technologies (ISCIT), 2013 13th International Symposium on

Conference_Location

Surat Thani

Print_ISBN

978-1-4673-5578-0

Type

conf

DOI

10.1109/ISCIT.2013.6645870

Filename

6645870