Efficiency of body biasing in 90 nm CMOS for low power digital circuits

Author

Von Arnim, Klaus ; Borinski, Eduardo ; Seegebrecht, Peter ; Fiedler, Horst ; Brederlow, Ralf ; Thewes, Roland ; Berthold, Jörg ; Pacha, Christian

Author_Institution

Corporate Res., Infineon Technol., Munich, Germany

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

175

Lastpage

178

Abstract

This paper presents an evaluation of body biasing, based on measured static and dynamic device performance. The efficiency of body biasing in sub-130 nm CMOS circuits strongly depends on the device type and operating temperature. While forward biasing still provides a significant performance gain in a 90 nm CMOS triple well process, the efficiency of reverse biasing nearly vanishes. The impact of the zero temperature coefficient point on low voltage digital circuit design is investigated.

Keywords

CMOS digital integrated circuits; integrated circuit design; leakage currents; logic design; low-power electronics; 90 nm; CMOS triple well process; forward body biasing; leakage reduction; low power digital circuits; operating temperature; reverse body biasing; zero temperature coefficient point; CMOS digital integrated circuits; CMOS logic circuits; CMOS technology; Digital circuits; Gate leakage; Leakage current; Logic devices; Subthreshold current; Temperature dependence; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European

Print_ISBN

0-7803-8480-6

Type

conf

DOI

10.1109/ESSCIR.2004.1356646

Filename

1356646