Gate Bias Instability in Polycrystalline Silicon Thin Film Transistors Formed Using Various Gate Dielectrics

Investigations have been made into the stability of polycrystalline silicon thin film transistors with respect to gate biasing. It is found that threshold voltage shifting occurs, and this is due to the tunnelling of electrons and holes into oxide traps, and to the drift of H⁺ and OH^-ions in the gate oxide. Results are presented for devices formed using a range of different polycrystalline silicon and silicon oxide materials.