Closed-loop control of gate-charge recycling in a 20 MHz dc-dc converter

Dynamic power consumption in the gate-drive circuitry limits the light-load efficiency of high frequency integrated dc-dc converters. In this paper a power MOSFET gate charge recycling technique is introduced, where the output capacitor is used to store a portion of the gate charge between switching events. The charge is transferred between the gate of power MOSFET and the output capacitor using transmission gates with precise timing control. The timing of the charge transfer is regulated using a simple digital delay-locked loop. The entire system is designed in 0.13 μm CMOS technology, and simulation results show a total saving of 25% in gate driver power and an overall efficiency improvement of 5% at light load. The converter operates at 20 MHz and converts 2.5 V to 0.8 ~ 1.6 V at up to 300 mA.