4-Mb MOSFET-selected phase-change memory experimental chip

Author

Bedeschi, F. ; Bez, R. ; Boffino, C. ; Bonizzoni, Edoardo ; Buda, E. ; Casagrande, G. ; Costa, L. ; Ferraro, Mario ; Gastaldi, R. ; Khouri, O. ; Ottogalli, F. ; Pellizzer, F. ; Pirovano, A. ; Resta, C. ; Torelli, G. ; Tosi, M.

Author_Institution

Memory Product Group, STMicroelectron., Agrate Brianza, Italy

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

207

Lastpage

210

Abstract

This paper presents a 4-Mb phase-change memory experimental chip using an MOS transistor as a cell selector. A cascode bit-line biasing scheme allows read and write voltages to be fed to the storage element with adequate accuracy. The chip was integrated with 3-V 0.18-μm CMOS technology and experimentally evaluated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to present NOR Flash memories. Cell current distributions on the 4-Mb array proved chip functionality and a good working window, thus demonstrating the feasibility of a stand-alone phase-change memory with standard CMOS fabrication process.

Keywords

MOS memory circuits; SRAM chips; order-disorder transformations; 0.18 micron; 3 V; 4 Mbit; 45 ns; 5 MB/s; CMOS technology; Ge₂Sb₂Te₅; MOS transistor cell selector; MOSFET-selected phase-change memory; OUM; PCM; cascode bit-line biasing scheme; cell current distributions; ovonic unified memories; read access time; storage element read voltage; storage element write voltage; write throughput; CMOS technology; Current distribution; Flash memory; MOSFETs; Phase change memory; Phased arrays; Semiconductor device measurement; Throughput; Time measurement; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European

Print_ISBN

0-7803-8480-6

Type

conf

DOI

10.1109/ESSCIR.2004.1356654

Filename

1356654