Sub-ns Delay Through Multi-Wall Carbon Nanotube Local Interconnects in a CMOS Integrated Circuit

A CMOS integrated circuit with multi-wall carbon nanotube (MWCNT) interconnects is presented, and its speed is analyzed. This chip is a platform to evaluate the merits of MWCNT interconnects in a silicon integrated circuit environment. Using this platform, we evaluate local interconnects (14¿m long) made of a single 30nm-diameter MWCNT. We experimentally extract the sub-ns delay of these wires to benchmark their future potential for the first time. Furthermore, we compare our experimental results with an existing MWCNT interconnect model, and discuss the origin of discrepancies.