Title :
A 97mW 110MS/s 12b pipeline ADC implemented in 0.18μm digital CMOS
Author :
Andersen, Terje N. ; Briskemyr, Atle ; Telsto, Frode ; Bjornsen, J. ; Bonnerud, T.E. ; Hernes, Bjsmar ; Moldsvor, Øystein
Author_Institution :
Nordic VLSI ASA, Trondheim, Norway
Abstract :
A 12 bit pipeline ADC, fabricated in a 0.18 μm pure digital CMOS technology, is presented. Its nominal conversion rate is 110 MS/s and the nominal supply voltage is 1.8 V. The effective number of bits is 10.4 when a 10 MHz input signal with 2 VP-P signal swing is applied. The occupied silicon area is 0.86 mm2 and the power consumption equals 97 mW. A switched capacitor bias current circuit scales the bias current automatically with the conversion rate, which gives scaleable power consumption and full performance of the ADC from 20 to 140 MS/s.
Keywords :
CMOS integrated circuits; analogue-digital conversion; low-power electronics; pipeline processing; switched capacitor networks; 0.18 micron; 1.8 V; 10 MHz; 2 V; 97 mW; automatic bias current scaling; conversion rate; digital CMOS; pipeline ADC; scaleable power consumption; switched capacitor bias current circuit; Capacitors; Degradation; Digital circuits; Energy consumption; Error correction; MOSFETs; Pipelines; Sampling methods; Switches; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European
Print_ISBN :
0-7803-8480-6
DOI :
10.1109/ESSCIR.2004.1356664
