DocumentCode
1905993
Title
Wafer zone based yield analysis
Author
Atchison, Nick ; Ross, Ron
Author_Institution
Silicon Syst. Inc., Santa Cruz, CA, USA
fYear
1997
fDate
6-8 Oct 1997
Abstract
The wafer fabrication process can produce both global problems that uniformly reduce the wafer probe yields and regionally distinct problems that reduce the yield of specific regions of the wafer. This paper discusses the methods used to develop simple programs capable of finding and reporting severity of low yielding wafer regions. Wafer regional yield trend graphs are explained and the comparative interpretation of yield trend changes is discussed. Finally, the methods used to correlate the regional yield changes to specific units of process equipment at specific process steps are briefly explained
Keywords
graphs; integrated circuit yield; probability; IC manufacture; low yielding wafer regions; process equipment; process steps; programs; wafer fabrication process; wafer regional yield trend graphs; wafer zone based yield analysis; Artificial intelligence; Computer aided manufacturing; Data analysis; Fabrication; Manufacturing processes; Mathematical analysis; Pattern analysis; Probes; Silicon; Spatial databases;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing Conference Proceedings, 1997 IEEE International Symposium on
Conference_Location
San Francisco, CA
Print_ISBN
0-7803-3752-2
Type
conf
DOI
10.1109/ISSM.1997.664591
Filename
664591
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