Efficient testability enhancement for combinational circuit

Author

Fang, Yu ; Albicki, Alexander

Author_Institution

Dept. of Electr. Eng., Rochester Univ., NY, USA

fYear

1995

fDate

2-4 Oct 1995

Firstpage

168

Lastpage

172

Abstract

We propose a novel testability enhancement scheme based on XOR Chain Structure. The structure is effective for improving both controllability and observability. The insertion points are selected by fast testability analysis and random pattern resistant node source tracking. Experiments with ISCAS85 benchmark circuits show that the scheme is effective. The incurred hardware overhead and performance penalty is relatively low

Keywords

VLSI; automatic testing; built-in self test; combinational circuits; logic testing; performance evaluation; ISCAS85; VLSI; XOR Chain Structure; automatic testing; benchmark circuits; combinational circuit testing; controllability; hardware overhead; insertion points; observability; performance penalty; random pattern resistant node source tracking; testability analysis; testability enhancement; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Controllability; Electrical fault detection; Observability; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1995. ICCD '95. Proceedings., 1995 IEEE International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-8186-7165-3

Type

conf

DOI

10.1109/ICCD.1995.528806

Filename

528806