DocumentCode
1906149
Title
Characterization and Matching Analysis of 50 nm-NMOS-Transistors
Author
Horstmann, J.T. ; Hilleringmann, U. ; Goser, K.
Author_Institution
Faculty of Electrical Engineering, University of Dortmund, Emil-Figge-Str. 68, D 44221 Dortmund, Germany, e-mail: horstman@luzi.e-technik.uni-dortmund.de
fYear
1996
fDate
9-11 Sept. 1996
Firstpage
253
Lastpage
256
Abstract
NMOS-transistors with a gate length down to 50 nm are fabricated by conventional optical lithography using a deposition and etchback technique. The local matching of the transistors is examined and compared to simulations. Finally the validity of the law of area (¿VT ¿ 1/ ¿W·L) for sub-100 nm-transistors will be discussed.
Keywords
Atomic measurements; Circuit analysis; Digital circuits; Etching; Fluctuations; Geometry; Optical films; Resists; Threshold voltage; X-ray lithography;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1996. ESSDERC '96. Proceedings of the 26th European
Conference_Location
Bologna, Italy
Print_ISBN
286332196X
Type
conf
Filename
5435234
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