A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS [ADC applications]

Author

Louwsma, Simon M. ; Van Tuijl, Ed J M ; Vertregt, Maarten ; Scholtens, Peter C S ; Nauta, Bram

Author_Institution

MESA+ Res. Inst., Twente Univ., Enschede, Netherlands

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

343

Lastpage

346

Abstract

A 1.6 GS/s track and hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is better than 2 ps and aperture uncertainty is less than 0.8 ps (RMS). The chip includes two analog to digital converters and a switching matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm², excluding the AD converters. The chip is made in a 0.12 μm, 1.2 V CMOS process. Power consumption of the interleaving T/H circuit is 32 mW.

Keywords

CMOS integrated circuits; UHF integrated circuits; analogue-digital conversion; buffer circuits; low-power electronics; sample and hold circuits; 0.12 micron; 1.2 V; 32 mW; 950 MHz; CMOS; ENOB; SFDR; aperture uncertainty; hold buffer; interleaved track-and-hold circuit; low power ADC; phase alignment; sampled output signal timing relations; switching matrix; voltage buffered output signals; Analog-digital conversion; Apertures; CMOS process; Circuits; Energy consumption; Interleaved codes; Matrix converters; Semiconductor device measurement; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European

Print_ISBN

0-7803-8480-6

Type

conf

DOI

10.1109/ESSCIR.2004.1356688

Filename

1356688