A cavity channel SESO embedded memory with low standby-power techniques

Author

Atwood, Bryan ; Ishii, Tomoyuki ; Watanabe, Takao ; Mine, Toshiyuki ; Kameshiro, Norifumi ; Sano, Toshiaki ; Yano, Kazuo

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

351

Lastpage

354

Abstract

A 22F² 3-transistor dynamic memory cell, based on a newly fabricated cavity channel SESO (single-electron shutoff) transistor is proposed for low-power mobile SOCs. The ultra-low leakage SESO device is formed above the bulk devices to yield the small cell size. With low-power techniques, this memory can achieve nearly an order of magnitude lower standby power than conventional memory. A 1 Mbyte SESO embedded memory core is estimated to have a standby power consumption of 24.2 μA in a 90 nm process.

Keywords

DRAM chips; leakage currents; low-power electronics; single electron transistors; system-on-chip; thin film transistors; 1 Mbyte; 24.2 muA; 3T-DRAM; 90 nm; cavity channel SESO transistor; dynamic memory cell; embedded memory; embedded memory core; low standby-power consumption; low-power mobile SOC; polysilicon TFT; single-electron shutoff transistor; small cell size; ultra-low leakage SESO device; Capacitors; Electron mobility; Energy consumption; Laboratories; Logic devices; Process design; Random access memory; Space technology; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European

Print_ISBN

0-7803-8480-6

Type

conf

DOI

10.1109/ESSCIR.2004.1356690

Filename

1356690