Title :
High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop]
Author :
Ishii, Kiyoshi ; Nosaka, Hideyuki ; Ida, Minoru ; Kurishima, Kenji ; Hirata, Michihiro ; Enoki, Takatorno ; Shibata, Tsugumichi
Author_Institution :
NTT Photonics Labs., NTT Corp., Kanagawa, Japan
Abstract :
We have designed and fabricated a high-bit-rate low-power decision circuit using InP/InGaAs heterojunction bipolar transistors (HBTs) with a cutoff frequency fT of approximately 150 GHz and a maximum oscillation frequency fmax of approximately 200 GHz. A novel master-slave D-type flip-flop (MS-DFF) circuit was used as the decision core circuit. The decision circuit operates approximately 15% faster than one with a conventional MS-DFF core. We achieved error-free operation at a data rate of up to 60 Gbit/s for the first time. The power consumption was only approximately 0.7 W, including that of the clock, data, and output buffers.
Keywords :
III-V semiconductors; bipolar MIMIC; bipolar integrated circuits; bipolar logic circuits; buffer circuits; decision circuits; flip-flops; gallium arsenide; heterojunction bipolar transistors; indium compounds; low-power electronics; 0.7 W; 150 GHz; 200 GHz; 60 Gbit/s; HBT; InP-InGaAs; MS-DFF; clock buffer; data buffer; heterojunction bipolar transistors; high-bit-rate decision circuit; low-power decision circuit; master-slave D-type flip-flop; output buffer; Circuits; Clocks; Cutoff frequency; Energy consumption; Error-free operation; Flip-flops; Heterojunction bipolar transistors; Indium gallium arsenide; Indium phosphide; Master-slave;
Conference_Titel :
Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European
Print_ISBN :
0-7803-8480-6
DOI :
10.1109/ESSCIR.2004.1356691
