Title :
Analysis of the transistor chain operation in CMOS gates for short channel devices
Author :
Chatzigeorgiou, A. ; Nikolaidis, S.
Author_Institution :
Dept. of Comput. Sci., Aristotelian Univ. of Thessaloniki, Greece
fDate :
31 May-3 Jun 1998
Abstract :
A detailed analysis of the transistor chain operation in CMOS gates is presented. The chain is diminished to a transistor pair taking into account the actual operating conditions of the structure. The output waveform is obtained analytically, without linear approximations of the output voltage and for ramp inputs. The α-power transistor current model which takes into account second order effects of submicron devices is used, while previous inconsistencies in the chain currents are eliminated by introducing a drain-to-source voltage modulation factor. The exact time when the chain starts conducting is efficiently calculated removing a major source of errors. The calculated output waveform results according to the proposed model are in excellent agreement with SPICE simulations
Keywords :
CMOS logic circuits; MOSFET; logic CAD; logic gates; semiconductor device models; α-power transistor current model; CMOS gates; drain-to-source voltage modulation factor; linear approximations; operating conditions; output voltage; output waveform; second order effects; short channel devices; submicron devices; transistor chain operation; transistor pair; Circuit simulation; Computer science; Integrated circuit modeling; Linear approximation; Parasitic capacitance; Physics; SPICE; Semiconductor device modeling; Timing; Voltage;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.705286
