Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM

Author

Jeong, Chunseok ; Yoo, Changsik ; Lee, Jae-Jin ; Kih, Joongsik

Author_Institution

Div. of Electr. & Comput. Eng., Hanyang Univ., Seoul, South Korea

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

379

Lastpage

382

Abstract

A digital delay locked loop (DLL) for 1.2 Gb/s/pin double data rate (DDR) SDRAM is described, which incorporates duty cycle correction (DCC). The DCC locking information is also stored as a digital code for fast wake-up from power-down mode and DCC control is done in an open-loop, enabling fast locking of the DCC loop with minimum additional power consumption. The DLL, implemented in a 0.35 μm CMOS technology, provides an output clock with 64 ps peak-to-peak jitter and the accuracy of the DCC is ±0.7% for ±10% input duty error from 250 MHz to 600 MHz clock frequency. The digital DLL, excluding I/O buffers, dissipates 10 mW from a 2.5 V power supply.

Keywords

CMOS digital integrated circuits; delay lock loops; low-power electronics; random-access storage; timing jitter; 0.35 micron; 1.2 Gbit/s; 10 mW; 2.5 V; 250 to 600 MHz; CMOS; DCC locking information storage; DDR SDRAM; DLL; I/O buffers; digital delay locked loop; double data rate SDRAM; low power consumption; open-loop digital duty cycle corrector; output clock jitter; power-down mode fast wake-up; CMOS technology; Clocks; DRAM chips; Data engineering; Delay lines; Energy consumption; Open loop systems; SDRAM; Timing; Uncertainty;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European

Print_ISBN

0-7803-8480-6

Type

conf

DOI

10.1109/ESSCIR.2004.1356697

Filename

1356697