• DocumentCode
    1906678
  • Title

    Improved Shallow Trench Isolation For Sub-Halfmicron CMOS

  • Author

    Cabanal, J.P. ; Haond, M.

  • Author_Institution
    CNET, Chemin du Vieux Chêne, BP 98, 38243 MEYLAN Cedex, FRANCE
  • fYear
    1991
  • fDate
    16-19 Sept. 1991
  • Firstpage
    651
  • Lastpage
    654
  • Abstract
    This paper presents new results on shallow trench isolation with the use of tilted field implants for avoiding the field parasitic transistors. Isolation results and gate oxide breakdown voltage are presented and discussed. The fabrication of 0.7 ¿m DLM 16K SRAMs with this type of isolation has been demonstrated with results similar to standard isolation circuits.
  • Keywords
    CMOS process; Circuits; Design engineering; Etching; MOS devices; MOSFETs; Microelectronic implants; Resists; Standards publication; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Device Research Conference, 1991. ESSDERC '91. 21st European
  • Conference_Location
    Montreux, Switzerland
  • Print_ISBN
    0444890661
  • Type

    conf

  • Filename
    5435252
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1906678