Title :
A Back - Biased 0.65 μm Leffn CMOS EEPROM Technology For Next - Generation Sub 7 ns Programmable Logic Devices
Author :
Hart, Michael J. ; Cacharelis, Philip J ; Carpenter, Roger D ; Tsuei, David G. ; Madurawe, Ramlnda U. ; Sandhu, Bal S. ; Smolen, Richard G. ; Dumlao, Andrew P. ; Garverick, Tim L. ; McFarlane, Thomas ; Manley, Martin H.
Author_Institution :
National Semiconductor Corporation, 2900 Semiconductor Drive, Santa Clara, CA 95052, USA.
Abstract :
A high-speed back-biased CMOS EEPROM technology and its application to Programmable Logic Devices (PLDs) will be described. Several key features have allowed the fabrication of a next generation high performance EECMOS PLD; the use of two independent families of transistors for the high voltage programming and read paths, the application of back-bias and careful optimisation of a double-polysilicon EEPROM cell. A sub 7 ns EECMOS PLD is described.
Keywords :
CMOS process; CMOS technology; EPROM; Fabrication; Low voltage; MOSFETs; Microelectronics; Programmable logic devices; Testing; Transistors;
Conference_Titel :
Solid State Device Research Conference, 1991. ESSDERC '91. 21st European
Conference_Location :
Montreux, Switzerland
