Title :
Hardware implementation of an artificial neural network
Author :
Botros, Nazeih M. ; Abdul-Aziz, M.
Author_Institution :
Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
Abstract :
A hardware implementation of a fully digital and fully interconnected feedforward backpropagation artificial network using Xilinx field programmable gate arrays (FPGAs) is presented. The network consists of an input layer with five nodes, a single hidden layer with four nodes, and an output layer with two nodes. These nodes are fully interconnected between adjacent layers. Training is done offline on a conventional digital computer where the final values of the weights are obtained. The network is tested successfully by comparing the values of the output nodes for a different input pattern with those obtained from simulating the network on a PC. The number of FPGAs used can be significantly decreased, and the speed can be increased if a 4K or higher family FPGA is used
Keywords :
backpropagation; feedforward neural nets; logic arrays; Xilinx field programmable gate arrays; artificial neural network; backpropagation; feedforward neural net; hidden layer; input layer; input pattern; output layer; speed; weights; Acceleration; Artificial neural networks; Computational modeling; Costs; EPROM; Feeds; Field programmable gate arrays; Neural network hardware; Testing; Very large scale integration;
Conference_Titel :
Neural Networks, 1993., IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-0999-5
DOI :
10.1109/ICNN.1993.298737
