Implementation of 2.6 Gbps super-high speed AES-CCM security protocol for IEEE 802.11i

This paper presents a memoryless, high throughput implementation of Advanced Encryption Standard Counter with Cipher Block Chaining Message Authentication Code (AES-CCM) for IEEE 820.11i, with a parallel architecture using two AES forward cipher modules. One AES cipher is used for calculating Message Integrity Check and another one for encrypting plaintext in generation-encryption mode or decrypting ciphertext in decryption-authentication mode. In this design, the forward AES cipher is implemented with reordering in iteration transformation to increase maximal period, while the SubByte function of the AES algorithm is completed in combinational logic. The AES-CCM ipcore is implemented in Synopsys CMOS SAED90nm. It performs throughput of 2.69 Gbps at 264 MHz and latency is 13 clock cycles.