DocumentCode
1907091
Title
Channel scaling in Si and In0.3 Ga0.7 As bulk MOSFETs: A Monte Carlo study
Author
Islam, Aynul ; Kalna, Karol
Author_Institution
Sch. of Eng., Swansea Univ., Swansea, UK
fYear
2010
fDate
13-14 June 2010
Firstpage
1
Lastpage
2
Abstract
The ITRS predicts that the scaling of planar CMOS technology will continue till the 22 nm technology node and a possible extension is extremely tempting. The desire to continue the scaling of planar technology is driven by lower costs when compared to novel, non-planar technology concepts like multi-gate architectures or nanowires. However, experimental evidence suggests that carrier effective mobility and injection velocity will dramatically lower at very small gate lengths thus prohibiting the possibility of reaching the ballistic regime.
Keywords
CMOS integrated circuits; MOSFET; Monte Carlo methods; ITRS; In0.3Ga0.7As; Monte Carlo study; bulk MOSFET; channel scaling; multigate architecture; nanowires; planar CMOS technology; Doping; Indium gallium arsenide; Logic gates; MOSFETs; Monte Carlo methods; Scattering; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Silicon Nanoelectronics Workshop (SNW), 2010
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4244-7727-2
Electronic_ISBN
978-1-4244-7726-5
Type
conf
DOI
10.1109/SNW.2010.5562543
Filename
5562543
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