High-speed forward error correction IP blocks for system-on-chip design

Author

Dinh, A.V. ; Bolton, R.J.

Author_Institution

Dept. of Electr. Eng., Saskatchewan Univ., Saskatoon, Sask., Canada

Volume

1

fYear

2002

fDate

2002

Firstpage

515

Abstract

High-speed forward error correction IP (intellectual property) blocks suitable for system-on-chip were designed for a wireless communications transceiver. Synthesizable HDL (hardware description language) code was written for the blocks including a differential encoder/decoder, a Reed-Solomon encoder/decoder and a convolutional interleaver/deinterleaver. The code was compiled, tested and verified for timing and function in both FPGA and 0.18 μm CMOS.

Keywords

CMOS digital integrated circuits; Reed-Solomon codes; application specific integrated circuits; codecs; convolutional codes; encoding; field programmable gate arrays; forward error correction; hardware description languages; industrial property; integrated circuit design; integrated circuit modelling; interleaved codes; transceivers; 0.18 micron; CMOS technology ASIC; FPGA; IP blocks; Reed-Solomon codec; Reed-Solomon encoder/decoder; SoC high-speed FEC intellectual property blocks; code compilation; code function verification; code testing; code timing verification; convolutional interleaver/deinterleaver; differential encoder/decoder; forward error correction; hardware description language code; synthesizable HDL code; system-on-chip; wireless communications transceivers; Convolutional codes; Decoding; Forward error correction; Hardware design languages; Intellectual property; Reed-Solomon codes; System-on-a-chip; Testing; Transceivers; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2002. IEEE CCECE 2002. Canadian Conference on

ISSN

0840-7789

Print_ISBN

0-7803-7514-9

Type

conf

DOI

10.1109/CCECE.2002.1015280

Filename

1015280