The Effects of Scaling and Rapid Thermal Annealing on the I/f Noise of Polysilicon Emitter Bipolar Transistors

Polysilicon Emitter Bipolar Transistor Technology is increasingly being used in modem VLSI for high speed applications [1]. An important feature of polysilicon emitter technology is that it lends itself to co-ordinated scaling of both vertical and lateral device dimensions. Therefore, devices with submicron feature sizes and emitter/base junctons shallower than 0.1¿m can be easily achieved. Another important advantage of polysilicon emitter bipolar transistors is that they offer significantly higher current gains compared with conventional bipolar transistors [2]. This feature makes polysilicon emitter technology very useful for analogue applications. For these applications the noise performance of the device, especially the Low Frequency (I/f) noise is a very important parameter.