The potential of poly-Si nanowire FETs featuring independent double-gated configuration for nonvolatile memory applications

Author

Chen, Wei-Chen ; Lin, Horng-Chih ; Huang, Tiao-Yuan

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2010

fDate

13-14 June 2010

Firstpage

1

Lastpage

2

Abstract

A simple and low-cost approach is proposed to fabricate SONOS devices featuring poly-Si nanowire (NW) and independent double-gated (IDG) structure. Making use of the separate-gated property, it is demonstrated that a proper auxiliary gate bias could enhance programming and erasing efficiency. 2-bit/cell operations can also be realized through two independent ONO storage sites. Such a high-performance poly-Si SONOS device with simple fabrication possesses strong potential for system-on-panel applications and 3D stacked high-density storage devices.

Keywords

field effect transistors; nanowires; polymers; random-access storage; silicon; 3D stacked high-density storage devices; IDG structure; ONO storage sites; SONOS devices; auxiliary gate bias; erasing efficiency; high-performance polysilicon SONOS device; independent double-gated configuration; nonvolatile memory applications; polysilicon nanowire FET; programming efficiency; separate-gated property; system-on-panel applications; Logic gates; SONOS devices; Thickness measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Nanoelectronics Workshop (SNW), 2010

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-7727-2

Electronic_ISBN

978-1-4244-7726-5

Type

conf

DOI

10.1109/SNW.2010.5562550

Filename

5562550