Title :
An area-efficient high-speed Reed-Solomon decoder in 0.25 μm CMOS
Author :
Strollo, A.G.M. ; Petra, N. ; De Caro, D. ; Napoli, E.
Author_Institution :
Dept. of Electron. & Telecom, Univ. of Naples "Federico II", Italy
Abstract :
In this paper, a Reed-Solomon (RS) decoder for the widely used (255, 239) code is presented. The circuit exploits both a novel inversion-free Berlekamp-Massey algorithm architecture to solve the key-equation and a new bit-parallel Galois-field multiplier implementation to obtain increased circuit speed. Hardware sharing is widely used to reduce silicon area occupation. The proposed circuit, designed for a 0.25 μm CMOS technology, compares favourably with recently proposed RS decoders.
Keywords :
CMOS digital integrated circuits; Galois fields; Reed-Solomon codes; decoding; 0.25 micron; CMOS; RS decoders; Reed-Solomon decoder; area-efficient high-speed decoder; bit-parallel Galois-field multiplier; hardware sharing; inversion-free Berlekamp-Massey algorithm; key-equation solution; CMOS technology; Circuits; Computer architecture; Decoding; Delay; Galois fields; Hardware; Polynomials; Reed-Solomon codes; Silicon;
Conference_Titel :
Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European
Print_ISBN :
0-7803-8480-6
DOI :
10.1109/ESSCIR.2004.1356723
