DocumentCode
1907385
Title
Investigation of 1T DRAM cell with non-overlap structure and recessed channel
Author
Kim, Sang Wan ; Kim, Garam ; Kim, Wonjoo ; Ko, Hyoungsoo ; Park, Byung-Gook
Author_Institution
Inter-Univ. Semicond. Res. Center (ISRC), Seoul Nat. Univ., Seoul, South Korea
fYear
2010
fDate
13-14 June 2010
Firstpage
1
Lastpage
2
Abstract
In this paper, a capacitor-less 1T DRAM cell transistor with non-overlap structure and recessed channel is presented. Because of the non-overlap structure between gate and source/drain, GIDL (Gate Induced Drain Leakage) current is efficiently suppressed at hold condition. This results in more than 1 s retention time at 25°C and 100 ms at 85°C.
Keywords
DRAM chips; capacitorless 1T DRAM cell transistor; gate induced drain leakage current; non-overlap structure; recessed channel; temperature 25 degC; temperature 85 degC; time 1 s; Electric potential; Junctions; Logic gates; Random access memory; Sensors; Simulation; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Silicon Nanoelectronics Workshop (SNW), 2010
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4244-7727-2
Electronic_ISBN
978-1-4244-7726-5
Type
conf
DOI
10.1109/SNW.2010.5562554
Filename
5562554
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