• DocumentCode
    1907471
  • Title

    Variability induced by Line edge roughness in silicon on thin box (SOTB) MOSFETs

  • Author

    Yang, Yunxiang ; Liu, Xiaoyan ; Du, Gang ; Han, Ruqi

  • Author_Institution
    Inst. of Microelectron., Peking Univ., Beijing, China
  • fYear
    2010
  • fDate
    13-14 June 2010
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    Statistical 3D TCAD simulations of 20nm gate SOTB MOSFETs have been done to study the effects of TBox, Vback-gate and WF on LER-induced variability. Our results show that thin box, reverse back-gate bias and high WF are effective ways to control the LER-induced threshold voltage´s variations, especially for n-SOTB MOSFETs.
  • Keywords
    MOSFET; nanotechnology; semiconductor device models; MOSFET variability; line edge roughness; silicon on thin box; size 20 nm; statistical 3D TCAD simulations; voltage ariation; Capacitance; Doping profiles; Logic gates; MOSFETs; Substrates; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Silicon Nanoelectronics Workshop (SNW), 2010
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-7727-2
  • Electronic_ISBN
    978-1-4244-7726-5
  • Type

    conf

  • DOI
    10.1109/SNW.2010.5562559
  • Filename
    5562559
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1907471