A new partitioning framework for uniform clock distribution during high-level synthesis

This weighted cluster partitioning technique is aided by an innovative resource allocation technique which provides a uniform resource utilization. This results in a uniform power requirement distribution across the synthesized chip which is practically beneficial as well. The resource cluster information obtained from this new partitioning synthesis framework could be used to aid the hierarchical placement and routing tools as well as the clock-router to design and produce a close to optimal uniform clock routing. This new framework applies the idea of local (intra-cluster) communication, while minimizing global communication busses. This resulted in a low-power design as well. The partitioner cost function considers three factors: the number of clock lines per unit area, the number of cuts between clusters, and the size of partitions. Experimental results show that this partitioning framework provides uniform clock distribution among clusters as well as fairly uniform sized partitions