A novel VLSI architecture for generation of Six Phase pulse compression sequences

Pulse compression technique is most widely used in Radar signal processing applications. For better pulse compression, peak signal to side lobe ratio i.e. merit factor should be as high as possible so that the unwanted clutter gets suppressed. To achieve the peaky main lobes and low side lobes, phase coded pulse compression codes are widely used. The simple phase code is obtained from the Binary phase coding. Matched filtering of biphase coded radar signals create unwanted side lobes which may mask important information. Hence the study of poly phase codes like Six phase pulse compression code is needed and the implementation techniques are carried out since the poly phase codes have low sidelobes and are better Doppler tolerant. The VLSI architectures for Phase coded Pulse compression systems described in the literature generate the pulse compression sequences with limited speed and consume more area on chip. But the real time implementation needs optimization of speed, area and power consumption. This paper concentrates on the design of an optimized model which can reduce these constraints. The proposed VLSI architecture can efficiently generate Six Phase pulse compression sequences while improving some of the parameters like area and speed when compared to previous methods. The VLSI architecture is implemented on the Field Programmable Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogrammability.