Gate CD control for a 0.35 μm logic technology

Author

Boynton, Terence ; Yu, Warren ; Pak, James

Author_Institution

Submicron Dev. Center, Adv. Micro Devices Inc., Sunnyvale, CA, USA

fYear

1997

fDate

6-8 Oct 1997

Lastpage

12

Abstract

To meet the demand for increased microprocessor performance while minimizing the loss due to excessively hot transistors, a comprehensive lithography methodology was implemented for improved gate CD control. Reduction in lot-to-lot CD variability was achieved by linking resist coaters, steppers, and developers into cells and through freezing of the process. Critical parameters were identified and monitored through SPC. A closed-loop system involving lithography and etch personnel provided added feedback on the lithography process control. The methodologies described in this paper led to improved gate-CD control with less than ±0.020 μm variability

Keywords

closed loop systems; integrated circuit technology; integrated logic circuits; photolithography; statistical process control; 0.35 micron; SPC; closed-loop system; developers; freezing; gate CD control; lithography methodology; logic technology; lot-to-lot CD variability; resist coaters; steppers; Condition monitoring; Etching; Feedback; Joining processes; Lithography; Logic; Microprocessors; Performance loss; Personnel; Resists;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing Conference Proceedings, 1997 IEEE International Symposium on

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-3752-2

Type

conf

DOI

10.1109/ISSM.1997.664597

Filename

664597