A DFT methodology targeting online testing of reversible circuit

Reversible logic is gaining importance for its ultra low power consumption. It has wide application in quantum computing, nanotechnology and optical computing. In this work, we propose a DFT (design for test) methodology for reversible logic blocks to enable online fault detection. A concurrent error detection technique, based on parity is introduced for the online testing. The methodology proposed for converting a 3×3 reversible gate into an online testable circuit ensures detection of all the stuck-at faults, bit flip faults and almost all multiple bit faults in logic blocks.