Title :
Sub-1 /spl mu/m/sup 2/ high density embedded SRAM technologies for 100 nm generation SOC and beyond
Author :
Tomita, K. ; Hashimoto, K. ; Inbe, T. ; Oashi, T. ; Tsukamoto, K. ; Nishioka, Y. ; Matsuura, M. ; Eimori, T. ; Inuishi, M. ; Miyanaga, I. ; Nakamura, M. ; Kishimoto, T. ; Yamada, T. ; Eriguchi, K. ; Yuasa, H. ; Satake, T. ; Kajiya, A. ; Ogura, M.
Author_Institution :
ULS1 Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
We have integrated a high speed and high density 6T-SRAM cell (0.998 /spl mu/m/sup 2/) for system-on-a-chip (SOC) using enhanced 100 nm CMOS logic technology. This is achieved by a systematic integration methodology, which includes high-NA ArF lithography, optimized optical proximity correction (OPC) CAD, narrow well isolation, poly-buffered shallow trench isolation (STI), offset spacer transistor, and 9-level Cu interconnect and low-k dielectric technologies with the lithographically scalable SRAM cell design.
Keywords :
CMOS memory circuits; SRAM chips; circuit CAD; dielectric thin films; high-speed integrated circuits; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; isolation technology; permittivity; photolithography; proximity effect (lithography); 100 nm; ArF; Cu; OPC; STI; SoC; enhanced CMOS logic technology; high density embedded SRAM technologies; high speed high density 6T-SRAM cell; high-NA ArF lithography; lithographically scalable SRAM cell design; narrow well isolation; nine-level Cu interconnect/low-k dielectric technologies; offset spacer transistor; optimized optical proximity correction CAD; poly-buffered shallow trench isolation; system-on-a-chip; systematic integration methodology; CMOS logic circuits; CMOS technology; Design optimization; High speed optical techniques; Integrated optics; Isolation technology; Lithography; Optical interconnections; Space technology; System-on-a-chip;
Conference_Titel :
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7312-X
DOI :
10.1109/VLSIT.2002.1015369
