Reduction of substrate-induced gate lag in GaAs MESFETs

Author

Jianwen Bao ; Leoni, R.E., III ; Xiaohang Du ; Hwang, J.C.M. ; Shah, D.M. ; Jones, J.R. ; Shokrani, M.L.

Author_Institution

Lehigh Univ., Bethlehem, PA, USA

fYear

1998

fDate

1-4 Nov. 1998

Firstpage

103

Lastpage

106

Abstract

Methods to suppress substrate trap-induced gate lag in ion-implanted GaAs MESFETs have been investigated in detail. It was found that the methods generally involve a supply of holes which can combine with the trapped electrons which are the culprits of gate lag. For high-power amplifiers employing high drain voltages, holes can be supplied through impact ionization. For battery-operated amplifiers employing low drain voltages, holes can be supplied through a contact to the buried p-layer.

Keywords

III-V semiconductors; Schottky gate field effect transistors; electron traps; gallium arsenide; impact ionisation; ion implantation; semiconductor device models; GaAs MESFET; buried p-layer contact; impact ionization; ion-implanted MESFET; substrate-induced gate lag reduction; trap-induced gate lag suppression; trapped electrons; Doping; Frequency; Gallium arsenide; Impact ionization; MESFETs; Monitoring; Pulse measurements; Resistors; Time measurement; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1998. Technical Digest 1998., 20th Annual

Conference_Location

Atlanta, GA, USA

ISSN

1064-7775

Print_ISBN

0-7803-5049-9

Type

conf

DOI

10.1109/GAAS.1998.722639

Filename

722639