Title :
Advanced Cu/low-k (k=2.2) multilevel interconnect for 0.10/0.07 /spl mu/m generation
Author :
Jang, S.M. ; Chen, Y.H. ; Chou, T.J. ; Lee, S.N. ; Chen, C.C. ; Tseng, T.C. ; Chen, B.T. ; Chang, S.Y. ; Yu, C.H. ; Liang, M.S.
Author_Institution :
Adv. Module Technol. Div., Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan
Abstract :
A spin-on dielectric (SOD, k=2.2) has been integrated with Cu for 0.10/0.07 /spl mu/m generations. To minimize interconnect capacitance, conventional CVD cap layer (k=4.5-7.5) is replaced by a SOD dielectric (k=2.9) and no stop layer for trench etch is used for the porous inter-metal dielectric (IMD). The issue of photoresist poisoning is resolved by nitrogen-free IMD processing. Using polymeric abrasive together with polishing parameters designed in a low friction domain for planarization, 6-level Cu/porous SOD multilevel interconnect is demonstrated for the first time. Electrical testing shows promising results for the high-performance dual damascene structure.
Keywords :
abrasion; capacitance; chemical mechanical polishing; copper; dielectric thin films; etching; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; photoresists; porous materials; spin coating; 0.07 micron; 0.1 micron; CVD cap layer; Cu; Cu/low-k multilevel interconnect; Cu/porous SOD multilevel interconnect; IMD; SOD dielectric; dual damascene structure; electrical testing; interconnect capacitance; low friction planarization domain; nitrogen-free IMD processing; photoresist poisoning; polishing parameters; polymeric abrasive; porous inter-metal dielectric; spin-on dielectric; technology generation; trench etch; Capacitance; Curing; Dielectric materials; Etching; Resists; Silicon carbide; Silicon compounds; Tensile stress; Testing; Thermal stresses;
Conference_Titel :
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7312-X
DOI :
10.1109/VLSIT.2002.1015371
