Title :
Fragile porous low-k/copper integration by using electro-chemical polishing
Author :
Takahashi, S. ; Tai, K. ; Ohtorii, H. ; Komai, N. ; Segawa, Y. ; Horikoshi, H. ; Yasuda, Z. ; Yamada, H. ; Ishihara, M. ; Nogami, T.
Author_Institution :
LSI Technol. Dev., Sony Corp., Kanagawa, Japan
Abstract :
A fragile porous ultra-low-k (k=2.2) silica was successfully integrated at trench level in damascene copper by applying our previously reported [1] electro chemical polishing (ECP) technique for Cu. After removing Cu by ECP, the barrier (WN) was removed by low pressure (LP) CMP (<1 psi). Practical polishing rates were obtained for WN in LP-CMP, because of higher chemical sensitivity of WN compared to Ta(N). Compatibility of CVD barrier to porous low-k, excellent barrier performance in aggressive features and lower via resistance were achieved by a newly developed CVD/PVD stacked WN barrier.
Keywords :
chemical interdiffusion; copper; dielectric thin films; diffusion barriers; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; permittivity; polishing; porous materials; silicon compounds; 1 psi; CVD barrier/porous low-k film compatibility; CVD/PVD stacked WN barrier; Cu-WN-SiO/sub 2/; ECP; WN barrier; barrier performance; chemical sensitivity; damascene copper; electro-chemical polishing; fragile porous low-k/copper integration; fragile porous ultra-low-k silica; low pressure CMP; polishing rates; trench level integration; via resistance; Atherosclerosis; Chemical processes; Chemical technology; Chemical vapor deposition; Copper; Dielectric materials; Electronic mail; Laboratories; Large scale integration; Silicon compounds;
Conference_Titel :
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7312-X
DOI :
10.1109/VLSIT.2002.1015376
