DocumentCode
1908254
Title
A 2.5 ns 8Ã\x978-b Parallel Multiplier Using 0.5 μm GaAs/GaAlAs Heterostructure Field Effect Transistors
Author
Berroth, M. ; Hurm, V. ; Nowotny, U. ; Hulsmann, A. ; Kaufel, G. ; Köhler, K. ; Raynor, B. ; Schneider, Jo.
Author_Institution
Fraunhofer-Institut f?r Angewandte Festk?rperphysik, D-7800 Freiburg, Germany.
fYear
1991
fDate
16-19 Sept. 1991
Firstpage
327
Lastpage
330
Abstract
To increase performance of GaAs LSI digital circuits, a 0.5 μm recessed gate process has been developed and utilized for an 8×8-b parallel multiplier. The chip contains about 3000 heterostructure field effect transistors and has a power consumption of 1.5 W. The best results of the maximum multiplication time measured were below 2.5 nsec.
Keywords
Automatic logic units; Digital circuits; Energy consumption; Gallium arsenide; HEMTs; Logic circuits; Logic design; Logic testing; MODFETs; Pulse inverters;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1991. ESSDERC '91. 21st European
Conference_Location
Montreux, Switzerland
Print_ISBN
0444890661
Type
conf
Filename
5435315
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