A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 /spl mu/m CMOS generation

Author

Oda, N. ; Ito, S. ; Takewaki, T. ; Kunishima, H. ; Hironaga, N. ; Honma, I. ; Namba, H. ; Yokogawa, S. ; Goto, T. ; Usami, T. ; Ohto, K. ; Kubo, A. ; Aoki, H. ; Suzuki, M. ; Yamamoto, Y. ; Watanabe, S. ; Takeda, T. ; Yamada, K. ; Kosaka, M. ; Horiuchi, T.

Author_Institution

ULSI Device Dev. Div., NEC Corp., Kanagawa, Japan

fYear

2002

fDate

11-13 June 2002

Firstpage

34

Lastpage

35

Abstract

A robust embedded ladder-oxide (k=2.9)/Cu multilevel interconnect is demonstrated for the 0.13 /spl mu/m CMOS generation. A stable ladder-oxide IMD is integrated into the Cu metallization with minimum wiring pitch of 0.34 /spl mu/m, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with SiO/sub 2/ IMD. The stress-migration lifetime of vias on wide metals for S/D Cu-plug structure is much longer than for dual damascene (D/D). The reliability test results such as those for electromigration (EM), Cu interconnect TDDB, and pressure cooker test (PCT) are quite acceptable. Moreover, high flexibility in thermal design and packaging is obtained.

Keywords

CMOS integrated circuits; VLSI; copper; dielectric thin films; electric breakdown; electromigration; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; internal stresses; permittivity; thermal stresses; 0.13 micron; 0.34 micron; CMOS generation; Cu; Cu interconnect TDDB; Cu metallization; SiO/sub 2/ IMD; dual damascene Cu-plug structure; electromigration test; minimum wiring pitch; packaging flexibility; pressure cooker test; reliability test; robust embedded ladder-oxide/Cu multilevel interconnect technology; single damascene Cu-plug structure; stable ladder-oxide IMD; thermal design flexibility; via stress-migration lifetime; wiring capacitance; CMOS technology; Capacitance; Integrated circuit interconnections; Metallization; Robustness; Samarium; Testing; Thermal conductivity; Thermal stresses; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7312-X

Type

conf

DOI

10.1109/VLSIT.2002.1015377

Filename

1015377