A stochastic computation based integer DCT implementation in HEVC

In this paper, a stochastic computation (SC) based hardware implementation for 4-point DCT in the emerging High Efficiency Video Coding (HEVC) standard was provided. HEVC employs integer DCT with larger transform coefficients than the preceding standards. Hence the multipliers and adders therein are also more hardware consuming. With SC theory applied to DCT hardware design, the circuit implementation is simplified. In DCT implementation the parallel architecture was adopted based on weighted binary generator to improve the whole computing throughput. The impact of different shift lengths on the accuracy of SC multiplier was also analyzed. Based on SC DCT, We propose a modified architecture which greatly improves the whole computing accuracy. The proposed two SC based DCTs are implemented on Xilinx FPGA. They both have more than 50% hardware resource saved and 2 times working frequency compared with traditional methods.