Integrating virtual platforms into a heterogeneous MoC-based modeling framework

In order to handle the increasing complexity of embedded systems, design methodologies must take into account important aspects, such as abstraction, IP-reuse and heterogeneity. System design often starts in a high abstraction level, by developing a virtual platform (VP), which is typically composed of TLM models. TLM has become very popular in the modeling of bus-based systems and currently there is an increasing availability of libraries that provide TLM IPs. Heterogeneity can be naturally captured in a framework supporting different Models of Computation (MoCs). We introduce a novel approach for integrating TLM IPs/VPs into a MoC-based modeling framework, allowing them to co-simulate heterogeneous systems. This approach allows to raise the abstraction level, enabling a more careful design space exploration before selecting a proper VP. We exemplify the potential of our approach with a case study in which a VP with a processor generated by ArchC communicates with a continuous-time model.