A detailed 3D-NEGF simulation study of tunnelling in n-Si nanowire MOSFETs

Author

Martinez, Antonio ; Seoane, Natalia ; Brown, Andrew R. ; Asenov, Asen

Author_Institution

Dept. Electron. & Electr. Eng., Univ. of Glasgow, Glasgow, UK

fYear

2010

fDate

13-14 June 2010

Firstpage

1

Lastpage

2

Abstract

Nanowire field-effect transistors (NWT) attract significant interest as strong contenders for future CMOS applications. Their superior electrostatic integrity offers ultimate-scaling solutions.The source-drain tunnelling increases leakage current but also enhances significantly the on-current, due to the narrowing of the source drain potential barrier at high drain voltage.Therefore the optimal design of nanowire MOSFETs in the near-ballistic regime of operation requires a careful trade off between the detrimental tunnelling-related increase of the leakage current in the sub-threshold regime and the enhancement of the on-current at large drain bias conditions.

Keywords

CMOS integrated circuits; MOSFET; nanowires; tunnelling; 3D-NEGF simulation study; CMOS applications; detrimental tunnelling-related increase; electrostatic integrity; high drain voltage; leakage current; nanowire MOSFET; nanowire field-effect transistors; source drain potential barrier; source-drain tunnelling; sub-threshold regime; ultimate-scaling solutions; Computational modeling; Electric potential; Electrostatics; Logic gates; MOSFETs; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Nanoelectronics Workshop (SNW), 2010

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-7727-2

Electronic_ISBN

978-1-4244-7726-5

Type

conf

DOI

10.1109/SNW.2010.5562591

Filename

5562591