Title :
A highly manufacturable 110 nm DRAM technology with 8F/sup 2/ vertical transistor cell for 1Gb and beyond
Author :
Akatsu, H. ; Weis, R. ; Cheng, K. ; Seitz, M. ; Kim, M.-S. ; Ramachandran, R. ; Dyer, T. ; Kim, B. ; Kim, D.-K. ; Malik, R. ; Strane, J. ; Goebel, T. ; Kwon, O.-J. ; Sung, C.Y. ; Parkinson, P. ; Wilson, K. ; McStay, I. ; Chudzik, M. ; Dobuzinsky, D. ; Jac
Author_Institution :
Semicond. R&D Center, IBM Microelectron., Hopewell Junction, NY, USA
Abstract :
This paper describes a 110 nm half-pitch DRAM technology utilizing an 8F/sup 2/ vertical transistor trench cell and optimized for ease of manufacturing and scaling. All four critical lithography steps are regular patterns in the array. High performance is provided through the use of tungsten word-lines, tungsten bit-lines, and the double-gated vertical array transistors. Area enhancement techniques in the trench capacitor allow the use of conventional dielectric materials into the 110 nm generation. A 512 Mb prototype chip has been fabricated using this technology.
Keywords :
DRAM chips; circuit optimisation; dielectric thin films; integrated circuit interconnections; integrated circuit manufacture; integrated circuit metallisation; isolation technology; photolithography; 1 Gbit; 110 nm; 512 Mbit; 8F/sup 2/ vertical transistor cell; DRAM scaling; DRAM technology; W; critical lithography steps; dielectric materials; double-gated vertical array transistors; half-pitch DRAM technology; manufacturability; prototype chip; regular array patterns; trench capacitor area enhancement techniques; tungsten bit-lines; tungsten word-lines; vertical transistor trench cell; Capacitance; Capacitors; Dielectric materials; Isolation technology; Lithography; Manufacturing; Random access memory; Silicon compounds; Transistors; Tungsten;
Conference_Titel :
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7312-X
DOI :
10.1109/VLSIT.2002.1015384
