Author :
Choi, S. ; Nam, B.Y. ; Ku, J.-H. ; Kim, D.C. ; Lee, S.H. ; Lee, J.J. ; Lee, J.W. ; Ryu, J.D. ; Heo, S.J. ; Cho, J.K. ; Yoon, S.P. ; Choi, C.J. ; Lee, Y.J. ; Chung, J.H. ; Kim, B.H. ; Lee, M.B. ; Choi, G.H. ; Kim, Y.S. ; Fujihara, K. ; Chung, U.I. ; Moon,
Author_Institution :
Semicond. R&D Div., Samsung Electron. Co. Ltd., Kyunggi, South Korea
Abstract :
Sub-100 nm DRAM is successfully fabricated for the first time with several key technologies, including W/W/sub x/N-poly gate, bitline structure having low parasitic capacitance, Ru/Ta/sub 2/O/sub 5//poly-Si capacitor and advanced CVD-Al contact processes. A fully functional working device is obtained with promising cell performance. Each technology also shows its extendibility as a manufacturable module process for further scaled DRAM.
Keywords :
DRAM chips; chemical vapour deposition; electrolytic capacitors; integrated circuit design; integrated circuit interconnections; integrated circuit manufacture; integrated circuit metallisation; nanotechnology; 100 nm; Al; CVD-Al contact processes; DRAM technology; Ru-Ta/sub 2/O/sub 5/-Si; Ru/Ta/sub 2/O/sub 5//poly-Si capacitor; W-WN; W/W/sub x/N-poly gate; bitline structure; cell performance; functional working device; functionality; manufacturable module process; parasitic capacitance; scaled DRAM; technology extendibility; Capacitance; Capacitors; Manufacturing; Moon; Random access memory; Space technology; Surface treatment; Temperature; Tin; Transistors;
