A 0.08 /spl mu/m/sup 2/-sized 8F/sup 2/ stack DRAM cell for multi-gigabit DRAM

Author

Hyunpil Noh ; Suock Jeong ; Seongjoon Lee ; Yousung Kim ; Woncheol Cho ; Min Huh ; Gucheol Jeong ; Jaebuhm Suh ; Hoyeop Kweon ; Jaesung Roh ; Kisoo Shin ; Sangdon Lee

Author_Institution

Memory R&D Div., Hynix Semicond. Co. Ltd., Kyungki, South Korea

fYear

2002

fDate

11-13 June 2002

Firstpage

56

Lastpage

57

Abstract

The first 8F/sup 2/ stack DRAM cell with 0.08 /spl mu/m/sup 2/ size has been successfully integrated by employing a poly plug scheme for landing plug contacts and W/poly gates and Ru MIM capacitors, of which cell working has been proven under easy function check mode. The cell transistor with W gate technology exhibits sufficient saturation current (I/sub OP/) of /spl sim/40 /spl mu/A with threshold voltage (V/sub tsat/) of 0.9 V and satisfactory ring oscillator delay characteristics of /spl sim/50 ps.

Keywords

DRAM chips; MIM devices; delays; electric current; electrical contacts; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; thin film capacitors; 0.9 V; 40 muA; 50 ps; 8F/sup 2/ stack DRAM cell; Ru; Ru MIM capacitors; W-Si; W/poly gates; cell transistor W gate technology; cell working; easy function check mode; landing plug contacts; poly plug scheme; ring oscillator delay characteristics; saturation current; threshold voltage; Contact resistance; Delay; Electrodes; Etching; Isolation technology; Lithography; MIM capacitors; Plugs; Random access memory; Ring oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7312-X

Type

conf

DOI

10.1109/VLSIT.2002.1015386

Filename

1015386