DocumentCode
1908588
Title
New technique of interlayer dielectric CMP with capping layer
Author
Ishimoto, Kohichi ; Tanaka, Shunsuke ; Kishimoto, Mitsugu ; Itoh, Yoshitake
Author_Institution
Dept. of Semicond. Oper., IBM Japan Ltd., Shiga, Japan
fYear
1997
fDate
6-8 Oct 1997
Abstract
A new technique of interlayer dielectric (ILD) planarization with chemical mechanical polishing (CMP) has been developed. The feature of this technique is to remove the step height more efficiently by making use of the polishing rate difference between two films deposited before CMP process. As compared to conventional process, the thickness of insulating layer before polishing can be reduced and the planarized surface can be obtained in shorter polishing time. This technique is one solution for CMP throughput and cost problem
Keywords
ULSI; integrated circuit interconnections; polishing; ULSI; capping layer; chemical mechanical polishing; double layer; efficient step height removal; interlayer dielectric planarization; polishing rate difference; removal thickness; throughput and cost problem; Chemical vapor deposition; Costs; Dielectrics; Glass; Insulation; Lithography; Planarization; Resists; Throughput; Ultra large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing Conference Proceedings, 1997 IEEE International Symposium on
Conference_Location
San Francisco, CA
Print_ISBN
0-7803-3752-2
Type
conf
DOI
10.1109/ISSM.1997.664601
Filename
664601
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