Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic

Low power consumption or high execution speed is achieved by making an application specific design. However, today´s systems also require flexibility in order to allow running similar or updated applications (e.g. due to changing standards). Finding a good trade-off between reconfigurability and performance is a challenge. This paper presents a tool that analyzes a given set of applications (as netlists) and generates a heterogeneous coarse-grain reconfigurable architecture that matches their requirements. Its main task is to optimize the interconnect by hierarchically grouping the functional units. Additional resources can be added to enable future applications. The tool generates the HDL source for a module with the instances of all blocks and the reconfigurable interconnect. The feasibility of the methodology is demonstrated by the design of a reconfigurable architecture for digital filters and simple logic networks.